1. Field of the Invention
The present invention relates to a data output apparatus and method of outputting data to a memory, a memory system having a memory device and memory controller, and a data processing method of the memory device in the memory system.
2. Description of the Related Art
Recently, the improvement of the semiconductor process has dramatically increased the integration degree and operating frequency of an LSI, and the performance of an apparatus using this LSI has also increased. The increase in operating frequency has also increased the electromagnetic radiation of an LSI, and makes it difficult to control EMI (Electro Magnetic Interference). When the operating frequency of an LSI rises, the amount of harmonic components at high frequencies contained in a clock signal increases, and this increases the radiation of the harmonic components.
An SSCG (Spread Spectrum Clock Generator) is used to control the EMI. The SSCG oscillates (modulates) the clock frequency of an LSI by slightly changing the frequency, thereby lowering the peak of the EMI.
As the operating frequency of an LSI increases, it is becoming important to ensure the quality of a signal, i.e., so-called signal integrity.
When a transistor on an LSI chip switches, a high-frequency electric current flows through a power supply/ground line and generates noise on it. This is so-called power bounce or ground bounce.
This noise increases in proportion to the number of transistors that switch. A large power bounce or ground bounce produced when a large number of transistors integrated on an LSI chip simultaneously switch is called SSO (Simultaneous Switching Output) noise.
The noise increases as the operating frequency and integration degree of an LSI increase. On the other hand, the noise margin decreases as the power supply voltage of an LSI lowers and its operating frequency increases. This makes it important to control the noise.
Japanese Patent Laid-Open No. 2004-213563 has proposed a memory access signal generator as the technique that effectively reduces the noise and EMI as described above.
In this memory access signal generator described in Japanese Patent Laid-Open No. 2004-213563, when the transition of a digital signal is detected and the signal is delayed, control is performed so as not to delay a digital signal in the next stage that has simultaneously detected the transition. In addition, control is performed so as to delay the digital signal in the next stage that has simultaneously detected the transition, thereby always controlling the number of simultaneous switching actions generated by a digital signal such as an address signal or data signal to ½. This makes it possible to appropriately reduce the power consumption, noise, and EMI.
Unfortunately, the memory access signal generator described in Japanese Patent Laid-Open No. 2004-213563 has the problem that if the number of times of data switching increases, noise increases, and the noise decreases the operation margin.